1. Field of the Invention
The present invention pertains generally to electronic circuits and, in particular, to amplifier circuits having a capacitor input which can be reset without disturbing the charge on the capacitor.
2. Related Art
Various amplifier circuits have been developed that utilize input capacitor to store a charge related to a signal to be amplified. Such amplifier circuits are commonly used in Analog-to-Digital Converters (ADCs). Analog-to-Digital Converters (ADCs) are becoming more common due to reduced cost of implementing such converters and due to the increase in use of digital circuitry. There is a class of ADCs, sometimes referred to as subranging ADCs, that utilizes a reduced number of comparator banks in order to reduce the component count. One form of the prior art subranging ADC is shown in FIG. 1. ADC 10, which utilizes what is commonly referred to as a unified architecture, includes a reference resistor network 12 for producing a large number of reference voltages. Typically, network 12 will include a number of resistors connected in series between an upper reference voltage Vref.sup.+ and a lower reference voltage Vref.sup.-. These reference voltages are compared to an analog input Vin in order to determine the magnitude of Vin relative to each of the reference voltages. This relative magnitude information is used to generate the digital output of the ADC. For an eight bit ADC, fifteen major tap points are provided on the network which are evenly spaced so as to provide fifteen different coarse reference voltages V.sub.RC. There are fifteen minor taps intermediate the major taps and intermediate the upper and lower reference voltages so as to produce a total of 240 fine reference voltages V.sub.RF.
As previously noted, ADC 10 operates to compare an input Vin to be digitized with the coarse and fine reference voltages V.sub.RC and V.sub.RF to provide a digital output based upon the comparison. A comparator bank 14 is used to carry out the comparisons. There are a total of 255 reference voltages so that a total of 255 comparator circuits would be required if conventional flash ADC architecture were used. However, since a subranging ADC having a unified architecture is used, bank 14 has only 15 comparator circuits. One of the 15 comparator circuits, circuit 14A, is shown in FIG. 2. Each comparator circuit receives three inputs, including the analog input Vin to be measured, one of the 15 coarse reference voltage V.sub.RC and one of the 240 fine reference voltage V.sub.RF. Switches S1A, S2 and S3 operate to sequentially connect one of the three inputs to the comparator circuits in accordance with the timing diagram of FIGS. 3A, 3B and 3C.
Comparator circuit 14A includes a pair of amplifiers 22 and 24 connected in series and driving a comparator/latch circuit 26 which provides a latched digital output. A capacitor C1 is connected in series between the input switches S1A, S2 and S3 and the input of amplifier 22. A second capacitor C2 is connected between the output of amplifier 22 and the input of amplifier 24.
Operation of ADC 10 begins with the closure of switches S1A, S1B and S1C as indicated by the waveform of FIG. 3A. Closure of switches S1B and S1C connect the respective outputs of amplifiers 22 and 24 to the respective inputs. This will cause each of the amplifier inputs to be set to the input threshold or virtual ground of the amplifiers so that a slight increase in input voltage will cause the inverting amplifier outputs to decrease and a slight decrease will cause the amplifier outputs to go higher. Capacitor C2 will hold a voltage equal to the difference in the threshold voltages of amplifiers 22 and 24. Capacitor C1 will hold a voltage equal to the difference in input voltage Vin and the threshold voltage of amplifier 22.
As shown in FIGS. 3A and 3B, switches S1A, S1B and S1C will open followed by closure of switch S2. It is standard procedure to open switch S1A after switches S1B and S1C have been opened. Note that since the input impedance of the amplifiers is high, there will be no change in charge on either capacitor C1 or C2. Switch S2 will connect the associated coarse reference voltage V.sub.RC to the input terminal of capacitor C1. Depending upon the magnitude of V.sub.RC relative to the input Vin, the voltage at the input of open loop amplifier 22 will increase above the threshold voltage or fall below the threshold voltage by an amount proportional to the difference in magnitude. This difference will be amplified by amplifier 22 and applied to the input terminal of capacitor C2. The amplified output will be applied to the input of amplifier 24. Since the charge on capacitor C2 is conserved, the input of amplifier 24 will increase above the threshold voltage of amplifier 24 or fall below the threshold voltage by an amount equal to the change in output of amplifier 22. Amplifier 24 will further amplify the difference voltage, with the output being coupled to a comparator/latch circuit 26. Comparator/latch circuit 26 will provide a compare operation and provide a digital output when strobed indicative of the magnitude of Vin relative to the associated coarse reference voltage V.sub.RC.
During normal operation, Vin will fall somewhere between Vref.sup.+ and Vref.sup.-, with those comparator circuits having associated values of V.sub.RC greater than Vin producing a "1" output and those having an associated value of V.sub.RC less than Vin producing a "0" output. An encoder 18 converts the 15 digital outputs to provide the four MSBs of the ADC by way of a demultiplexer 20. The two adjacent comparator circuits 15 having digital outputs which transition from a "1" to a "0" will have associated values of V.sub.RC which bracket the magnitude of Vin. This means that input Vin falls somewhere within the range defined by the 15 fine reference voltages V.sub.RF which fall intermediate the two associated values of V.sub.RC. Encoder 18 provides a control signal to multiplexer 16, causing the multiplexer to select the appropriate group of fine reference voltages V.sub.RF from the 16 groups of fine reference voltages.
Once the appropriate group of fine reference voltages V.sub.RF has been selected, multiplexer 16 will have connected one of the 15 different values of V.sub.RF to each of the 15 comparator circuits 14A. There is a delay between the opening of switch S2 and the closure of switch S3, as indicated by FIGS. 3B and 3C, to provide time for the compare operations to take place. The charge on capacitors C1 and C2 will have remained unchanged, with the charge on capacitor C1 continuing to be the difference between Vin and the input threshold voltage of amplifier 22. Accordingly, the output of amplifier 24 will reflect an amplified difference in magnitude between Vin and the selected fine reference voltage V.sub.RF. Latch circuit 26 will store a digital value which corresponds to the amplified difference. Encoder 18 will encode the 15 different latch outputs and provide 4 bits which will correspond to the 4 LSBs of the ADC thereby concluding the conversion for one value of Vin.
The unified architecture of FIG. 1 is capable of providing a relatively large number of bits of resolution using a small number of comparator circuits. Thus, the cost of manufacturing the ADC is reduces, as is the power consumption. However, the unified architecture has certain drawbacks, one of which relates to the speed of operation.
There is an increased demand for higher speed operation of ADCs while maintaining a low component count. The present invention permits higher speed operation of ADCs utilizing the unified architecture while still maintaining the advantages inherent in the architecture. This and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention.